Field of the Invention
The present invention relates to an electronic endoscope apparatus for supplying a multi-valued drive signal, which is higher than a ternary value, to a solid imaging device so as to create a feed-through period for the purpose of eliminating noise in the output signal from the solid imaging device.
Recently, an optical endoscope has been widely used which allows observation of diseased areas of the coelom and, if necessary, aids in medical treatment of the diseased areas with a treatment device by allowing the insertion of an elongated portion, thus obviating an incision.
An electronic or electron endoscope without the image guide of the above-described optical endoscope but having a solid imaging device such as a CCD (a Charge Coupled Device) at the position of the focal plane of an object lens thereof has been put into practical use.
The electron endoscope of the type described above constitutes an electron endoscope apparatus comprising a light source which is employed similarly to that of the above-described optical endoscope, a signal processing device and display means.
FIG. 1 illustrates an electron endoscope apparatus 1 according to a first conventional example.
The electron endoscope apparatus 1 shown in FIG. 1 comprises: an electron endoscope (to be abbreviated to "an electron scope" hereinafter) 2A including imaging means; a video processor 5 including a light source portion 3 for supplying illumination light to the electron scope 2A and a signal processing portion 4 for processing signals to be supplied to the electron scope 2A; and a monitor 6 for displaying the video signal which has been processed in the signal processing portion 4, the video signal being displayed in the form of an image.
The above-described electron scope 2A has an elongated portion 7 to be inserted into the coelom. A light guide 8 for transmitting illumination light and inserted into the elongated portion 7 has a light incidental terminal connected to the light source portion 3 so that illumination light is supplied through the light guide 8. White light, emitted from a lamp 11 disposed in the light source portion 3, is converted into successive light consisting of red, green and blue by a rotary filter 12 having color transmissive filters for the three primaries: red, green and blue and allowing the white light to pass through. Light thus converted is converged by a convergent lens 13 so as to be supplied, as illumination light, to the light incidental surface of a light guide 8. The above-described rotary filter 12 is arranged to be rotated by a motor 14.
Red, green and blue illumination light transmitted through the light guide 8 is emitted from the light-emitting surface of the light guide to a subject 15. Light reflected from the subject 15 forms an image of the subject 15 on the imaging surface of a CCD17A disposed on the focal plane of an object lens 16 fastened to the end portion of the portion 7 to be inserted into the coelom. The CCD17A photoelectrically converts the image thus formed so as to store it as a signal charge.
The above-described CCD17A is arranged to receive power from a power source 23 via a power supply line 21 and a ground line 22 respectively connected to a power source terminal VDD and a ground terminal SUB adjacent to the video processor 5.
The level of a vertical transfer clock .phi.p transmitted from a drive signal generating circuit 24' is changed by a driver 25. The waveform of the vertical transfer clock .phi.p whose level has been changed is then shaped by a matching circuit 26 constituted by a capacitor C and a resistor R. The vertical transfer clock .phi.p whose waveform has been shaped is then transmitted to the CCD17A via a vertical transfer clock transmitting cable (to be abbreviated to "a .phi.p transmitting cable" or "a .phi.p cable" hereinafter) 27.
The drive signal generating circuit 24A also generates a horizontal transfer clock .phi.s the voltage level of which is then changed by a driver 28. The waveform of the horizontal transfer clock .phi.s the voltage level of which has been changed is then shaped by a matching circuit 29 constituted by a capacitor C and a resistor R. It is then transmitted to the CCD17A via a horizontal transfer clock transmitting cable (to be abbreviated to "a .phi.s transmitting cable" or "a .phi.s cable" hereinafter) 30.
The drive signal generating circuit 24A also generates a blooming control clock .phi.AB the voltage level of which is then changed by a driver 31. The waveform of the blooming control clock .phi.AB the voltage level of which has been changed is then shaped by a matching circuit 32 constituted by a capacitor C and a resistor R. It is then transmitted to the CCD17A via a blooming control clock transmitting cable (to be abbreviated to "a .phi.AB transmitting cable" or "a .phi.AB cable" hereinafter) 33.
As shown in FIG. 2, optical information imaged on the CCD17A is photoelectrically converted so as to be stored in each of pixels 34 as a charge. At this time, blooming is prevented by the blooming control clock .phi.AB. The charge thus stored is transferred vertically by the vertical transfer clock .phi.p in a direction designated by an arrow so that it reaches a horizontal transfer register 35. The charge in the horizontal transfer register 35 is transferred horizontally by a quantity corresponding to one pixel due to an addition of the horizontal transfer clock .phi.s so as to be supplied, as an output from the CCD17A, to a buffer transistor 36.
Then, a state where the signal is transmitted from the CCD17A will be described in detail with reference to FIG. 3.
The horizontal transfer clock .phi.s transfers the charge stored in the horizontal transfer register 35 to a charge detection circuit 37 (a synthetic capacity of a floating diffusion layer 38 constituted by N channels and the gate and line capacity of a MOS transistor 39 where the synthetic capacity being abbreviated to "an FDA" hereinafter). Furthermore, the horizontal transfer clock .phi.s turns on a reset transistor 40 so as to reset the FDA. In the case, the operation is performed as shown in FIG. 4.
As shown in FIG. 4A, the FDA is reset when the horizontal transfer clock .phi.s is at the high level, while the charge of the horizontal transfer register 35 is transferred to the FDA when the horizontal transfer clock .phi.s is at the low level.
As shown in FIG. 4B, the waveform of a signal Vout transmitted from the buffer transistor 36 is in the form consisting of only reset periods and charge detection periods and having no feed-through period which corresponds to zero charge at this time. Referring to FIG. 4B, the hatched section shows a CCD charge detection level.
As described above, the output signal Vout from the CCD17A and transmitted via the buffer transistor 36 is further transmitted through a Vout (a transmitting) cable 42 via a matching resistor 41 of the cable. The Vout cable 42 is introduced into a video signal processing circuit 45A disposed in the video processor 5 together with a noise-cancelling dummy cable 44 grounded via a resistor 43 having the same resistance level as that of a matching resistance 41 disposed adjacent to the CCD17A.
In the video signal processing circuit 45A, the difference is obtained between the output signal Vout from the above-described CCD 17 and a dummy signal V.sub.DUMMY from the noise cancelling dummy cable 44, that is the difference from inductive noise on the cable 44 so as to convert the thus obtained difference into a TV signal, the TV signal thus converted being then transmitted to the monitor 6. Thus, the endoscope image obtained by the electron scope 2 is displayed on the monitor 6.
According to the above-described first conventional example, since a sole signal .phi.s is employed so as to serve as both the clock for horizontally transferring the charge in the horizontal transfer register 35 and the clock for turning of/off the transistor which resets the FDA, a so-called feed-through period is not present in the waveform of the output signal Vout as shown in FIG. 4B.
Therefore, it is impossible for the reset noise and 1/f noise contained in the output signal Vout to be eliminated in the video signal processing circuit 45A in the video processor 5 by using a correlation double sampling (to be abbreviated to "CDS" hereinafter) circuit.
Then, a second conventional example will be described with reference to FIGS. 5 to 8.
The difference from the above-described first conventional example lies in a structure arranged in such a manner that a different signal from the horizontal transfer clock is used so as to serve as the clock for resetting the FDA.
FIG. 5 illustrates the overall structure of the second conventional example, where the difference from the first conventional example lies in the structure arranged to be (capable of transmitting a reset drive signal .phi.R.
The reset clock .phi.R generated in a drive signal generating circuit 24B is changed in its voltage level by a driver 46 before it has been shaped by a matching circuit 47 consisting of a capacitor C and a resistor R. It is then transmitted to a CCD 17B via a reset clock transmitting cable (to be abbreviated to "a .phi.R transmitting cable" or "a .phi.R cable, hereinafter) 48.
A state in which a signal is transmitted from the CCD 17B via the FDA will be described with reference to FIGS. 6 and 7.
In the CCD 17B, a terminal for the horizontal transfer clock .phi.s and that of the reset clock .phi.R are independently provided so that the clocks .phi.s and .phi.R respectively shown in FIGS. 7B and 7A are supplied to the corresponding terminals. That is, although the charge, which has been horizontally transferred by the horizontal transfer clock .phi.s, is transferred to the FAD, the FDA is reset at a timing shown in FIG. 7A prior to the above-described transference of the charge.
Therefore, as shown in FIG. 7C, the output signal Vout from the CCD 17B contains a period in which the FDA is reset, a charge-detection period in which the charge is transferred from the horizontal transfer register to the FDA and the charge thus transferred is detected, and the other period between the above-described two periods. That is, there is a period in which no charge is transferred from the horizontal transfer register to the FDA and the FDA is not reset, that is, a feed-through period corresponding to a so-called zero charge is present in the output signal Vout from the CCD 17B.
Thus, the video signal processing circuit 45B can be allowed to cancel reset noise and 1/f noise in the output signal Vout by using the CDS circuit. As a result, an excellent image can be obtained.
However, there arises a necessity to provide the .phi.R cable 48 so as to serve as a cable. Therefore, in the case of the electron scope 2B, there arises a necessity of enlarging the outer diameter of the electron scope 2B, causing the outer diameter of the front portion to be enlarged. Therefore, the patient feels pain at the time of insertion of the enlarged front portion of the electron scope 2B, or the use of the electron scope of this time is limited.
As described above, although the outer diameter of the scope 2A is not enlarged in the structure according to the first conventional example, noise contained in the output signal from its CCD cannot be eliminated.
On the other hand, since the feed-through period is contained in the output signal from its CCD, noise contained in the output signal can be eliminated by using the CDS circuit. However, a signal cable must be additionally provided, causing the outer diameter of the scope 2B to be enlarged.